WED9LC6816V
White Electronic Designs
FIG. 13 SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ
BURST STOP @ BURST LENGTH = FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE
SDRAS#
SDCAS#
ADDR
RAa
CAa
CAb
BA0, 1
[A12,A13
]
RAa
SDA10
Note 2
1
1
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
QAa0 QAa1
QAa3 QAa4
QAa2
CL=2
CL=3
DQ
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
SDWE#
BWE#
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
Burst Stop
DON’T CARE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is the same as the case of SDRAS# interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on each
of them. But at burst write, burst stop and SDRAS# interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle”.
3. Burst stop is valid at every burst length.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
22
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
