WED9LC6816V
White Electronic Designs
FIG. 9 SDRAM PAGE READ CYCLE AT DIFFERENT BANK @
BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
Note 1
SDCE#
SDRAS#
SDCAS#
ADDR
Note 2
RAa
CAa RBb
CBb
CAc
CBd
CAe
BA0, 1
[A12,A13]
RAa
RBb
SDA10
QAa0 QAa1 QAa2
QBb3
QBb0 QBb1 QBb2
QAc0 QAc1
QBd0 QBd1 QAe0 QAe1
QAa3
CL=2
DQ
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 Qbb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
CL=3
SDWE#
BWE#
Read
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
Row Active
(B-Bank)
Precharge
(A-Bank)
DON’T CARE
Read
(A-Bank)
NOTES:
1. SDCE# can be “don’t care” when SDRAS#, SDCAS# and SDWE# are high at the clock going high edge.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
18
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
