WED9LC6816V
White Electronic Designs
FIG. 12 SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @
BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
SDCAS#
ADDR
BA0, 1
Ra
Rb
Ca
Cb
[A12,A13
]
Ra
Rb
SDA10
CL=2
Qa0
Db0
Db0
Db1 Db2
Db3
Qa1 Qa2 Qa3
DQ
CL=3
Qa0 Qa1
Qa3
Db1
Db2
Db3
Qa2
SDWE#
BWE#
Row Active
(A-Bank)
Auto Precharge
Start Point
(B-Bank)
Write with
Auto Precharge
(B-Bank)
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(B-Bank)
DON’T CARE
NOTES:
1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2 and BRSW mode)
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
21
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
