WED9LC6816V
White Electronic Designs
FIG. 14 SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND &
WRITE BURST STOP @ BURST LENGTH = FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
SDCAS#
ADDR
RAa
CAa
CAb
BA0, 1
[A12,A13
]
RAa
SDA10
DQ
tBDL
tRDL
Note 2
DAa0 DAa1 DAa2 DAa3 DAa4
DAb0 DAb1 DAb2 DAb3 DAB4 DAb5
SDWE#
BWE#
Write
(A-Bank)
Row Active
(A-Bank)
Burst Stop
Precharge
(A-Bank)
Write
(A-Bank)
DON’T CARE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. BWE# at write interrupt by
precharge command is needed to prevent invalid write.BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of
burst. Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
23
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
