WED9LC6816V
White Electronic Designs
FIG. 11 SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @
BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
SDCAS#
ADDR
BA0, 1
RAa
CAa
RBb
CBb
RAc
CAc
[A12,A13
]
RAa
RBb
RAc
SDA10
CL=2
tCDL
Note 1
QAa0
DBb0 DBb1
DBb0 DBb1
DBb3
QAc0 QAc1 QAc2
QAc0 QAc1
QAa1 QAa2 QAa3
QAa0 QAa1 QAa2
DBb2
DBb2
DQ
CL=3
QAa3
DBb3
SDWE#
BWE#
Write
(B-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
DON’T CARE
Row Active
(A-Bank)
Row Active
(A-Bank)
NOTES:
1. tCDL should be met to complete write.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
20
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
