WED9LC6816V
White Electronic Designs
FIG. 16
SDRAM MODE REGISTER
SET CYLE
SDRAM AUTO REFRESH CYCLE
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
9
10
SDCK
HIGH
SDCE#
Note 2
tRFC
SDRAS#
Note 1
Note 3
SDCAS#
ADDR
Key
Ra
DQ
HI-Z
HI- Z
SDWE#
BWE#
MRS
New
Comman d
Auto Refres h
New Comman d
DON'T CARE
*Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle.
NOTES:
MODE REGISTER SET CYCLE
1. SDCE#, SDRAS#, SDCAS# & SDWE# activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new SDRAS# activation.
3. Please refer to Mode Register Set Table.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
25
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
