WED9LC6816V
White Electronic Designs
FIG. 10 SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @
BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
Note 2
SDCAS#
ADDR
RAa
CAa RBb
CBb
CAc
CBb
BA0, 1
[A12,A13
]
SDA10
DQ
RAa
RBb
tCDL
tRDL
DAa3
DBb1 DBb2 DBb3 DAc0 DAc1
DBd1
DAa0 DAa1 DAa2
DBb0
DBd0
SDWE#
BWE#
Note 1
Row Active
(A-Bank)
Write
(A-Bank)
Row Active
(A-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
Write
(B-Bank)
Write
(A-Bank)
DON’T CARE
NOTES:
1. To interrupt burst write by Row precharge, BWE# should be asserted to mask invalid input data.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
19
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
