WED9LC6816V
White Electronic Designs
FIG. 15 SDRAM BURST READ SINGLE BIT WRITE CYCLE @
BURST LENGTH = 2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
SDCAS#
ADDR
RAa
CAa
RBb CAb
RAc
CBc
CAd
BA0, 1
]
[A12,A13
RAa
RBb
RAc
SDA10
CL=2
DAa0
DAa0
QAb0
DBc0
DBc0
QAd1
QAb1
QAd0
DQ
CL=3
QAd0 QAd1
QAa1 QAb1
SDWE#
BWE#
Row Active
(A-Bank)
Precharge
(Both Banks)
Row Active
(A-Bank)
Read
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Row Active
(B-Bank)
Read with
Write
Auto Precharge
(A-Bank)
(A-Bank)
DON’T CARE
NOTES:
1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at Write is fixed to “1” regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in
the case of BRSW write command, the next cycle starts the precharge.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
24
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
