WED9LC6816V
White Electronic Designs
FIG. 8 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @
BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
tRCD
SDRAS#
Note 2
SDCAS#
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA0, 1
[A12,A13
]
Ra
SDA10
CL=2
tRDL
Qa0
Qa1
Qb1
Qb2
Dc0
Dc0
Dc1
Dd1
Qb0
Dd0
DQ
t
CDL
Qa3
Dc1
Dd0 Dd1
Qa0 Qa1 Qa2
CL=3
SDWE#
BWE#
Note 3
Note 1
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
DON’T CARE
NOTES:
1. To write data before burst read ends. BWE# should be asserted three cycle prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.
3. BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked
internally.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
17
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
