WED3DL644V
White Electronic Designs
FIG. 12 READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP
@BURST LENGTH=FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CE#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA
RAa
A10/AP
Note 3
1
QAa0 QAa1 QAa2 QAa3 QAa4
1
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL = 2
DQ
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL = 3
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
DON'T CARE
NOTES:
1.
2.
At full page mode, burst is end at the end of burst. So auto precharge is possible.
About the valid DQs after burst stop, it is same as the case of RAS# interrupt.
Both cases are illustrated in above timing diagram. See the label 1, 2.
But at burst write, Burst stop and RAS# interrupt should be compared carefully.
Refer to the timing diagram of "Full page write burst stop cycle."
Burst stop is valid at every burst length.
3.
August 2005
Rev. 6
21
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