WED3DL644V
White Electronic Designs
FIG. 10 READ & WRITE CYCLE WITH AUTO PRECHARGE @BURST LENGTH=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CE#
RAS#
CAS#
ADDR
Ra
Rb
Ca
Cb
BA
Ra
A10/AP
Rb
CL = 2
DQ
Qa0
Qa1
Qa2
Qa1
Qa3
Db0
Db0
Db1
Db2
Db3
CL = 3
Qa0
Qa2
Qa3
Db1
Db2
Db3
WE#
DQM
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
Row Active
(B-Bank)
DON'T CARE
NOTE:
1.
t
CDL should be controlled to meet minimum tras before internal precharge start.
(in the case of Burst Length=1 & 2 and BRSW mode)
August 2005
Rev. 6
19
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
