WED3DL644V
White Electronic Designs
FIG. 9 READ & WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CE#
RAS#
CAS#
ADDR
RAa
RBb
CBb
CAa
RAc
CAc
BA
RAa
A10/AP
RBb
RAc
tCDL
Note 1
CL = 2
DQ
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2
QAc0 QAc1
CL = 3
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write
(B-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Row Active
(A-Bank)
DON'T CARE
NOTE:
1.
t
CDL should be met to complete write.
August 2005
Rev. 6
18
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
