WED3DL644V
White Electronic Designs
FIG. 8 PAGE WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
BA
A10/AP
DQ
RAa
RBb
tCDL
tRDL
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1
WE#
Note 1
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Write
(A-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
Write
(A-Bank)
DON'T CARE
NOTES:
1.
2.
To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
August 2005
Rev. 6
17
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
