WED3DL644V
White Electronic Designs
FIG. 15 ACTIVE/PRECHARGE POWER DOWN MODE @CAS LATENCY=2, BURST LENGTH=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
Note 2
tSS
tSS
tSS
Note 1
CKE
Note 3
CE#
RAS#
CAS#
ADDR
Ra
Ca
BA
A10/AP
DQ
Ra
tSHZ
Qa0
Qa1
Qa2
WE#
DQM
Precharge
Power-Down
Entry
Row Active
Precharge Active
Power-Down Power-Down
Exit Entry
Precharge
Read
Active
DON'T CARE
Power-Down
Exit
NOTES:
1.
2.
3.
Both banks should be in idle state prior to entering precharge power down mode.
CKE should be set high at least 1 CK + tSS prior to Row active command.
Cannot violate minimum refresh specification (64ms).
August 2005
Rev. 6
24
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