VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
VSC8025/VSC8026
Figure 5: VSC8025 Clock and Data Interface (Contra-directional & Co-directional Mode)
VSC8025
PM5355/PM5312
TXCLK+
TXCLK-
TXINA[7:0]
Divide-
by-8
Q D
Q D
TXPCLKIN+
TXPCLKIN-
TXFPIN[A:D]
TXCLKIN
Q D
Q D
1
0
SELPCLK
Divide-
by-4
TXCLK12A
Refer to Note (6)
SYNCRSTB
(A). Contra-directional Mode Interface
VSC8025
PM5355/PM5312
TXINA[7:0]
TXCLK+
TXCLK-
Divide-
by-8
Q D
Q D
Q D
TXPCLKIN+
TXPCLKIN-
TXFPIN[A:D]
TXCLKIN
Q D
SELPCLK
0
1
Divide-
by-4
TXCLK12[A:D]
Refer to Note (6)
SYNCRSTB
TXOOF
Q
S
77.76MHz Clock
R
Refer to Note (4)
(B). Co-directional Mode Interface
Note: 1. TXINB [7:0], TXINC [7:0], and TXIND [7:0] inputs have been omitted for simplicity.
2. TXCLK12B, TXCLK12C, and TXCLK12D output have been omitted for simplicity.
3. In contra-directional mode, TRISE=TFALL=logic “0”.
4. In co-directional mode, TRISE=logic “1”; TFALL=logic “1” when not using TSYNC, logic “0” if using TSYNC.
5. In co-directional mode, the 77.76MHz input clock to PM5355/PM5212 must be blocked out for at least 32 cycles
when SYNCRSTB transitions low (logic “0”) due to misalignment of TXFPIN[A:D] as shown in Figure 3.
6. SYNCRSTB, a TTL output with a minimum VOH of 2.4V, needs to be buffered up to drive the reset pins of the PMC
parts. RSTB and TRSTB on the PM5355/PM5312 have a minimum VIH of 3.5V.
G52182-0, Rev. 4.0
VITESSE SEMICONDUCTOR CORPORATION
Page 9
1/5/00
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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