VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
VSC8025/VSC8026
data stream. This frame pulse is aligned with the first payload byte in every STS-48/STM-16 frame. Data on
TXPOUT[7:0] and TXFPOUT is clocked out on the rising edge of TXPCLKOUT+ (refer to Figure 9).
When only the parallel STS-48/STM-16 output port is used, e.g. when the VSC8025 is used to feed an
STS-192/STM-64 MUX, the VSC8025 does not have to be supplied with a 2.488 GHz clock, since the serial
output mux is not used. Instead, a 311.04 MHz clock can be provided on the TXPCLKIN differential ECL input
pins. The asynchronous SELPCLK input needs to be held high to select the TXPCLKIN clock source. Refer to
Figure 21 for a detailed equipment loopback diagram.
Facility Loopback
To create a facility (or line) loopback, the VSC8025 is equipped with a high-speed clock (TXSLBCLK)
and data (TXSLBIN) input. TXSLBIN is captured on the falling edge of TXSLBCLK+ (refer to Figure 8) and
clocked out through the TXSOUT port on the falling edge of TXSCLKOUT+ (refer to Figure 7), when the
asynchronous FACLOOP input is held high. Refer to Figure 21 for a detailed facility loopback diagram.
STS-48c Mode
To support STS-48c operation, where bytes from the four STS-12/STM-4 inputs are interleaved on at a
time (as opposed to four at a time in STS-48 mode), the byte interleaver can be configured for STS-48c multi-
plexing by holding the asynchronous SELSTS48C input high.
Scrambler
The VSC8025 performs optional scrambling using a frame synchronous scrambler with generating polyno-
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mial 1 + x + x and a sequence length of 127. The scrambler is disabled by asserting input DISSCRM high.
DISSCRM is latched-in once every frame by a valid frame pulse.
Error Performance (B1)
The bit interleaved parity byte B1 is calculated over the entire scrambled STS-48/STM-16 frame and
inserted into the B1 location of the next frame before scrambling. The B1 generation can be disabled by setting
DISB1GEN input high. DISB1GEN is latched-in once every frame by a valid frame pulse.
Section-Trace Insertion (J0/Z0)
The section-trace bytes (J0/Z0) can optionally be filled by setting the SETJZ[1:0] as indicated in Table 1.
When SETJZ[1:0] is held at ‘00’, the J0/Z0 bytes will be passed on transparently. For SETJZ[1:0] at ‘01’ an
increasing binary value of 01\hex to 30\hex fill the J0/Z0 bytes. Since the first section-trace byte J0 could carry
a section-trace message it can be passed on transparently while the Z0 bytes are set to an increasing binary
number from 02\hex to 30\hex by setting SETJZ[1:0] to ‘10’. The last mode SETJZ[1:0] = ‘11’ allows for a
transparent J0 byte and CC\hex filled Z0 bytes.
M1/B2 Modification
When multiplexing four STS-12/STM-4 SONET/SDH frames into one STS-48/STM-16 frame, the M1
byte of the outgoing STS-48/STM-16 frame must be calculated from the four M1 bytes contained in the STS-
12/STM-4 frames. The VSC8025 extracts the M1 bytes from the four STS-12/STM-4 input frames, adds them
together (and truncates to 255, if the sum is larger), and inserts the result in the M1 byte of the STS-48/STM-16
G52182-0, Rev. 4.0
VITESSE SEMICONDUCTOR CORPORATION
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