VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
VSC8025/VSC8026
Figure 3: VSC8025 Synchronous Reset Timing Diagram
TXCLK12[A:D]
TXFPIN0
16 cycles
16 cycles
16 cycles
TXFPIN1
TXFPIN2
TXFPIN3 misaligned
TXFPIN3
SYNCRSTB
TXOOF
Note: DISFPCHK = DISBLC12 = logic ‘0’.
Table 1: VSC8025 Section-Trace Insertion Select Settings
SETJZ[1]
SETJZ[0]
Function
0
0
1
1
0
1
0
1
Transparent
01\hex-30\hex
J0 Transparent, Z0:02-30\hex
J0 Transparent, Z0:CC\hex
Table 2: VSC8025 Input Timing Mode Select Settings
Mode
Contra-Directional
TRISE
TFALL
TSYNC
TXCLKIN
0
0
0
TXCLK12
External
77.76 MHz
signal
Co-Directional
Adjust clock only after RESET
1
1
1
0
0
Co-Directional
Adjust clock after RESET and after
rising edge on TSYNC
External
77.76 MHz
signal
External
Signal
G52182-0, Rev. 4.0
1/5/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 7
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