VITESSE
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
SEMICONDUCTOR CORPORATION
Datasheet
VSC8025/VSC8026
Table 7: VSC8025 Parallel Data Output Timing (Equipment Loopback)
Parameter
Description
Parallel transmit clock period
Min
Type
Max
Units
TTXPCLKOUT
-
3.215
-
ns
Delay from rising edge of TXPCLKOUT+ to
valid data on TXPOUT [7:0] and on TXFPOUT
TPSKEW
0.1
-
1.3
ns
Figure 9: VSC8025 Parallel Data Output Timing Diagram (Equipment Loopback)
TTXPCLKOUT
TXPCLKOUT+
TXPCLKOUT-
TPSKEW
TXPOUT[7:0]
TXFPOUT
Note: Duty cycle for TXPCLKOUT is 50% ± 10% when configured for serial output mode (SELPCLK=Ø)
Duty cycle for TXPCLKOUT depends on TXPCKLIN duty cycle when configured for parallel output only (SELPCLK=1)
VSC8025 Power Dissipation
Table 8: VSC8025 Power Supply Currents (Outputs Open)
Parameter
Description
(Max)
Units
ITT
ITTL
IDD
PD
Power supply current from VTT
Power supply current from VTTL
Power supply current from VDD
Power dissipation
2.12
103
A
mA
A
0.48
7.44
W
Page 12
VITESSE SEMICONDUCTOR CORPORATION
G52182-0, Rev. 4.0
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
1/5/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
