VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
VSC8025/VSC8026
Table 5: VSC8025 Serial Data Output Timing
Parameter
Description
Serial Transmit clock period
Min
Type
Max
Units
TTXSCLKOUT
-
401.9
-
ps
Delay from falling edge of TXSCLKOUT+ and valid
data on TXSOUT
TSSKEW
20
-
140
ps
Figure 7: VSC8025 Serial Data Output Timing Diagram
TTXSCLKOUT
TXSCLKOUT+
TXSCLKOUT-
TSSKEW
TXSOUT+
TXSOUT-
Table 6: VSC8025 Serial Data Input Timing (Facility Loopback)
Parameter
Description
Serial loopback clock period
Min
Typ
Max
Units
TTXSLBCLK
-
401.9
-
ps
Serial loopback input data TXSLBIN setup time with
respect to falling edge of TXSLBCLK+
TTXLSU
TTXLSH
120
60
-
-
-
-
ps
ps
Serial loopback input data TXSLBIN hold time with
respect to falling edge of TXSLBCLK+
Figure 8: VSC8025 Serial Data Input Timing Diagram (Facility Loopback)
TTXSLBCLK
TXSLBCLK-
TXSLBCLK+
TTXLSU TTXLH
TXSLBIN+
TXSLBIN-
G52182-0, Rev. 4.0
1/5/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 11
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