VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
VSC8025/VSC8026
Mux/Demux and Section Terminator IC Chipset
Table 3: VSC8025 Serial Clock Input Timing
Parameter
Description
High speed input clock period
High speed input clock duty cycle
Min
Typ
Max
Units
TTXCLK
DTXCLK
-
401.9
50
-
ps
%
45
55
Table 4: VSC8025 Parallel Data Input Timing
Parameter
Description
Min
Typ
Max
Units
TTXCLK12
DTXCLK12
TTXCLKIN
DTXCLKIN
TJITTER
Divide-by-32 output clock period
Divide-by-32 output clock duty cycle
Parallel input data load clock period
Parallel input data load clock duty cycle
TXCLKIN jitter
-
12.86
50
-
55
-
ns
%
ns
%
ns
45
-
12.86
50
40
60
2
TXIN[A:D][7:0], TXFPIN[A:D], and TXIN[A:D]P data
setup time with respect to rising edge of TXCLKIN
TTXPSU
TERR
0.35
1.7
-
-
-
ns
ns
Propagation delay from rising edge of TXCLKIN to
TXPER[A:D]
6.8
TXIN[A:D][7:0], TXFPIN[A:D], and TXIN[A:D]P data
hold time with respect to rising edge of TXCLKIN
TTXPH
1.1
-
-
-
-
ns
ns
TCSKEW
TXCLK12[A:D] clock skew
0.67
Maximum allowable propagation delay for connecting
TX12CLKA to TXCLKIN in Contra-Directional Mode
(TRISE=TFALL=logic ‘0’, TTXCLK12 = typ)
TPROP
-
-
6
ns
Figure 6: VSC8025 Parallel Data Input Timing Diagram
TTXCLK12
TXCLK12[A:D]
TPROP
TTXCLKIN
TXCLKIN
TTXPSU TTXPH
TXINA[7:0]
TXINB[7:0]
TXINC[7:0]
TXIND[7:0]
TXFPIN[A:D]
TXIN[A:D]P
TERR
TXPER[A:D]
Page 10
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52182-0, Rev. 4.0
1/5/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
