VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
VSC8025/VSC8026
VSC8025 Package Pin Description
Table 9: Pin Identification Table
Signal
Pin
I/O
Level
Pin Description
VSCTE
N/C
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
C01
C02
C03
I
-2.0
Test Enable (tie to -2V)
No Connection (tie to 0V or leave open)
-2.0V power supply
VTT
PWR
-2V
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
GND
TTL
TTL
TTL
TXPERD
TXPERB
TXPERA
TXINDP
TXINCP
TXCLK12D
TXCLK12C
TXCLK12B
NOFP
O
Parallel input bus D parity error
Parallel input bus B parity error
Parallel input bus A parity error
Parallel input bus/frame pulse D parity
Parallel input bus/frame pulse C parity
Transmit clock divided by 32
Transmit clock divided by 32
Transmit clock divided by 32
No frame pulse detected (active high)
Synchronous reset when not byte aligned (active low)
Ground
O
O
I
I
O
O
O
O
SYNCRSTB
VCC
O
PWR
TXIND5
TXINC7
SETJZ1
N/C
I
I
I
Parallel input bus data D
Parallel input bus data C
Section trace byte control
No Connection (tie to 0V or leave open)
No Connection (tie to 0V or leave open)
Disable M1/B2 circuitry (active high)
Disable blocking of TXCLK12 (active high)
Parallel input bus C parity error
Ground
N/C
DISM1GEN
DISBLC12
TXPERC
VCC
I
TTL
TTL
TTL
GND
TTL
TTL
GND
TTL
TTL
TTL
TTL
TTL
TTL
GND
TTL
I
O
PWR
TXINBP
TXINAP
VCC
I
Parallel input bus/frame pulse B parity
Parallel input bus/frame pulse A parity
Ground
I
PWR
TXOOF
TXIND7
TXIND6
TXIND4
TXFPIND
TXINC5
VCC
O
Transmit out of frame (active high)
Parallel input bus data D
I
I
Parallel input bus data D
I
Parallel input bus data D
I
Transmit frame pulse in (active high)
Parallel input bus data C
I
PWR
I
Ground
SETJZ0
N/C
Section trace byte control
No Connection (tie to 0V or leave open)
G52182-0, Rev. 4.0
1/5/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 13
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