VITESSE
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
SEMICONDUCTOR CORPORATION
Datasheet
VSC8025/VSC8026
frame. The M1 bytes of the STS-12/STM-4 frames are simultaneously nulled (00\hex is inserted). The errors
introduced into the B2 bytes by this M1 modification are also corrected.
The M1/B2 circuitry can be disabled by holding the asynchronous input DISM1GEN high.
Parity
An even parity input is provided for each byte wide data bus and respective frame pulse on TXIN[A:D]P.
The parity inputs are captured on the rising edge of TXCLKIN and compared with parity calculated internally.
Any resulting errors are clocked out by TXCLKIN on TXPER[A:D]. Parity errors are reported one cycle
delayed from input data. For no parity errors to result, the parity input for the bus must be logic 1 when an odd
number of bits in the byte wide data and frame pulse are logic 1; otherwise, it must be logic 0.
Figure 2: VSC8025 Functional Timing Diagram
TXCLKIN
TXINA[7:0]
TXINB[7:0]
TXINC[7:0]
TXIND[7:0]
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
DA1
DB1
DC1
DD1
DA2
DB2
DC2
DD2
DA3
DB3
DC3
DD3
DA4
DB4
DC4
DD4
DA5
DB5
DC5
DD5
TXFPIN[3:0]
TXPCLKOUT
TXPOUT[7:0]
(STS-48 Mode)
Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 DA1 DA2 DA3 DA4 DB1 DB2 DB3 DB4 DC1 DC2 DC3 DC4 DD1 DD2 DD3 DD4
TXFPOUT
TXSCLKOUT
DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4
b7 b6 b5 b4 b3 b2 b1 b0
TXSOUT
TXPOUT[7:0]
(STS-48c Mode)
Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 DA1 DB1 DC1 DD1 DA2 DB2 DC2 DD2 DA3 DB3 DC3 DD3 DA4 DB4 DC4 DD4
Note:
(1) The correct latency between TXINA-D, TXPOUT and TXSOUT is NOT shown.
(2) TXPOUT is equivalent to TXSOUT (byte wide). TXFPOUT is not applicable to serial output TXSOUT.
(3) MSB leads on TXSOUT; MSB is bit 7 on the TXINA-D inputs and TXPOUT outputs.
Page 6
VITESSE SEMICONDUCTOR CORPORATION
G52182-0, Rev. 4.0
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
1/5/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
