VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
VSC8025/VSC8026
Mux/Demux and Section Terminator IC Chipset
Input Synchronization
The four STS-12/STM-4 input data streams must be frame-aligned prior to being fed into the VSC8025.
The frame pulses TXFPIN[A:D] (active high) associated with each of the four STS-12/STM-4 data streams are
used to initiate and verify the frame-synchronization. These frame pulses must be aligned with the first payload
byte of the STS-12/STM-4 frames. The byte-interleave mux will be reset on the occurrence of the first valid
frame pulse on TXFPIN[A:D]. A valid frame pulse will only be detected if all four TXFPIN[A:D] inputs are
high at the same time. In the event that TXFPIN[A:D] are not exactly aligned to each other, a ‘reset sequence’
will be generated by the VSC8025 to re-synchronize the four STS-12/STM-4 input frames (refer to Synchro-
nous Reset Timing Diagram, Figure 3). The ‘reset sequence’ is designed specifically to a setup where the four
STS-12/STM-4 inputs are being driven from four PM5312/PM5355s. SYNCRSTB is asserted low for sixteen
77.76 MHz (TXCLK12) clock cycles. TXCLK12 outputs will be held low (blocked) during these sixteen cycles
and for an additional sixteen cycles thereafter if DISBLC12 is low, if DISBLC12 is high TXCLK12 outputs are
not blocked. TXOOF will be held high for sixteen TXCLK12 cycles after the TXCLK12 clocks start running
again to indicate that the CPU needs to reload the registers in the four PM5312/PM5355s. The ‘reset sequence’
circuitry can be disabled by asserting the asynchronous DISFPCHK input high. Once a valid frame pulse has
been detected, the VSC8025 performs additional frame alignment checks with the results indicated on output
NOFP. When DISFPCHK is set to logic “0”, NOFP goes high to indicate mis-alignment between the VSC8025
internal frame counter and a valid frame pulse (TXFPIN[A:D] = 1). NOFP will go high for minimum of 13.4uS
for this mis-alignment condition. When NOFP occurs, frame synchronization can only be established by reset-
ting the VSC8025. The VSC8025 will re-establish frame synchronization on the next valid frame pulse follow-
ing the reset. Typically, some external controller, operating off a clock which is not derived from the VSC8025,
should monitor NOFP and perform the appropriate reset when detected. When DISFPCHK is set to logic “1”,
NOFP behaves as described above with the exception that NOFP will go high if any of the four frame pulses is
missing when expected.
Input Timing Modes
There are two methods for driving TXCLKIN (clock signal associated with the byte-wide STS-12/STM-4
input ports). The first method, referred to as contra-directional, simply drives the input clock TXCLKIN and the
PMC devices (PM5312 or PM5355) using the output clock TXCLK12A. In this mode, there is a maximum
delay bound between the TXCLK12 output and the TXCLKIN input (see Figure 5). The second method,
referred to as co-directional, uses an externally generated 77.76 MHz source to drive TXCLKIN; TXCLK12s
can be used. This mode assumes no phase-relation between the TXCLKIN input and the TXCLK12 outputs
(contrary to contra-directional timing mode - see Figure 5), but does assume a frequency lock to the 2.5GHz
(serial) or 311MHz (parallel) clock.
In co-directional mode, internal clocking is adjusted to the external clock TXCLKIN shortly after a
RESET; and, if enabled, shortly after a rising edge on the TSYNC input. Input data may be missed during a
clock adjustment, so the frequency of updates should be kept low. See Table 2 to determine pin connections for
input data clocking modes (also reference Figure 4 and Figure 5, and application notes)
Equipment Loopback
The VSC8025 is equipped with a parallel output port which can be used for an equipment loopback by con-
necting it to the parallel STS-48/STM-16 input port on the VSC8026. This port can also be used to feed an
STS-192/STM-64 MUX. TXFPOUT contains a frame pulse synchronized with the parallel STS-48/STM-16
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VITESSE SEMICONDUCTOR CORPORATION
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