VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
VSC8025/VSC8026
VSC8025 Functional Description
The VSC8025 multiplexer serializes four byte-wide STS-12/STM-4 data streams into a 2.488 Gb/s serial
STS-48/STM-16 data stream and generates selected transmission frame section overhead bytes. The VSC8025
performs B1 calculation, scrambling and section-trace insertion. A functional block diagram of the VSC8025 is
shown in Figure 1.
The part is clocked by a 2.488 GHz clock, which has to be provided by an external source to TXCLK. The
VSC8025 is equipped with a 155.52 MHz differential ECL output clock, RCLK155, to facilitate the creation of
an external PLL circuit. Byte-wide data is presented to the TXINA[7:0], TXINB[7:0], TXINC[7:0] and
TXIND[7:0] input ports (e.g. originating from four PM5312/PM5355s) and is captured on the rising edge of
TXCLKIN (refer to Figure 6). Each of the four PM5312/PM5355s output a frame pulse aligned to the first pay-
load byte of every frame, as shown in the functional timing diagram, Figure 2. These frame pulses are connected
to TXFPIN[A:D] and are used for verifying that the four STS-12/STM-4 input data streams are synchronized
(refer to Input Synchronization below). TXFPIN[A:D] is captured on the rising edge of TXCLKIN. The four
STS-12/STM-4 data streams are byte-interleaved consistent with existing requirements for SONET/SDH inter-
mediate level multiplexing. Section-trace bytes, J0/Z0, and Section Error Performance byte, B1, are inserted,
the data stream is scrambled and serialized. The serial STS-48/STM-16 data stream is presented at the differen-
tial output, TXSOUT, on the falling edge of TXSCLKOUT+ (refer to Figure 7).
Figure 1: VSC8025 Functional Block Diagram
RESET
DISM1GEN
DISSCRM
SELSTS48C
DISB1GEN
CONTROL
RCLK155+/-
SETJZ[1:0]
TXPCLKOUT+/-
TXFPOUT
TXPOUT[7:0]
TXPER[A:D]
TXIN[A:D]P
TXINA[7:0]
REG/
PARITY
CHECK
SECTION
TRACE
INSERTION
+
TXINB[7:0]
TXINC[7:0]
TXIND[7:0]
INT
TXSOUT+/-
TXSCLKOUT+/-
SCRAMBLER
B1
8:1
M1/B2
MUX
TXSLBIN+/-
TXSLBCLK+/-
MOD.
FACLOOP
TXCLK+/-
CALCULATION
TXCLKIN
TRISE
TFALL
TSYNC
INPUT
TIMING
CONTROL
0
1
311 MHz INTERNAL
CLOCK SOURCE
TXFPIN[A:D]
TXCLK12[A:D]
SYNCRSTB
TXOOF
TXPCLKIN+/-
SELPCLK
FRAME
SYNC
CHECK
NOFP
DISFPCHK
DISBLC12
G52182-0, Rev. 4.0
1/5/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
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