Advance Product Information
Subject to Change
VSC7111 Datasheet
Functional Descriptions
Table 5.
Power State of Inputs and Outputs in Static Mode (continued)
MUXCFG = 1 MUXCFG = 0 and SCK = 0
MUX/fanout Non-PCIe buffer
MUXCFG = 0 and SCK = 1
I/O
mode
mode
PCIe buffer mode
Y1/Y1N Always ON
Y2/Y2N Always ON
Y3/Y3N Always ON
Not (FLOS1)
Not (FLOS2)
Not (FLOS3)
Always ON
Always ON
Always ON
2.4
Two-Wire Serial Interface, Slave Mode
When activated by a code of IFMODE[1:0] = 00, the chip enters two-wire slave serial
mode. The VSC7111 supports a slave mode two-wire serial interface, in which an
external master device controls the VSC7111 slave device. The two-wire serial interface
operates in both standard mode (up to 100 kbps) and fast mode (up to 400 kbps) data
transfer rates.
A master device generates a start condition <S> by transitioning SDA high to low while
SCK is high. Data is then transferred on the SDA line with the most significant bit (MSB)
first and the SCK line clocking each bit. Data transitions occur when the SCK is low and
is valid (read) or stable (write) when on the high to low transition of the SCK. Data
transfers are acknowledged (ACK or <A>) by the receiving device (VSC7111) for data
writes (and the master device for data reads) by holding the SDA signal low while
strobing SCK high then low. The master generates a stop condition <P> (terminates
the data transfer) with a low to high transition on the SDA signal while SCK is high. For
more information, see Figure 9, page 48.
Serial Write A serial write starts with the master sending a byte to the VSC7111. The
first seven bits represent the serial interface address, and the eighth must be a 0 to
indicate a write operation. The VSC7111 compares its serial interface address (set by
the SA[3:0] or the Serial Address register) to the one transmitted. An acknowledge is
generated only if they match. Without issuing a start or stop condition, the master then
sends a second byte to the VSC7111. The VSC7111 interprets this byte as the register
address. Finally, the master sends a third byte to the VSC7111. This is interpreted as
the data for the register write. At this point, the write has taken effect.
The following is an example of the write sequence, assuming the serial interface
address is set to 00'h:
One byte write: <S><00'h><A><Address><A><Data><A><P>
Serial Read A read cycle starts out similarly to the serial write, but immediately after
the desired register address (the second byte) is sent, a stop condition is issued. The
master then sends the serial interface address again, but this time uses a 1 in the LSB
to indicate a read operation. After the acknowledge cycle from the VSC7111, the
master stops driving the SDA line. At this point, the VSC7111 outputs one bit at a time
on the falling edge of SCK, transmitting the MSB first until eight bits are transmitted.
After the eighth falling edge of the SCK, the VSC7111 releases control of the SDA bus
and the master issues the clock for the acknowledge cycle. After the master issues the
acknowledge cycle, the master issues a stop condition, which signals the end of the
transmission.
Revision 2.0
September 2010
Confidential
Page 15
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
