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Subject to Change
VSC7111 Datasheet
Functional Descriptions
2.2
Page-Based Programming
The VSC7111 uses page-based register programming by means of two-wire or
four-wire serial interface to configure the features and functions of the device. Pages
are grouped according to function; each page typically has a maximum of four
addresses, but has a potential address space of 128 8-bit words. The register address
within each page corresponds to the number of the input or output that it controls. A
specific page is selected by programming the value for the desired page into the
Current Page register (address 7F'h).
The Current Page register and all other registers with an address of 50'h or higher are
not linked to a specific page, and can be programmed regardless of the value in the
Current Page register (address 7F'h). These registers are used to set features and
functions of the VSC7111 globally, by either setting all four registers in an associated
page with a single programming step, or by setting a configuration that affects the
operation of the entire device. For more information about these registers and their
functions, see “Registers,” page 25.
2.3
Static (Pin-Strap) Configuration
Input/output connections, equalization settings, buffer or MUX/fanout modes, low-
power modes, and PCIe receiver detection can be configured statically by strapping
pins high/low or by means of register programming. The state of the IFMODE1 and
IFMODE0 pins determines the configuration method, where 11 = static (pin-strap)
configuration, 00 = two-wire slave programming, 10 = two-wire master programming,
and 01 = four-wire serial programming. The following section describes the static
configuration method.
In static configuration, each input will squelch the output(s) to which it is connected
when LOS is detected. This feature enables applications such as SAS/SATA out-of-band
(OOB) signaling and PCI Express electrical idle. Also, when LOS is detected for more
than 1 ms at an input, the input will be shut down to save power. This cannot be
changed in the static configuration.
The MUXCFG pin determines the input to output connections. MUXCFG = 0 is the buffer
mode where each input is connected straight through to the corresponding output (A0
to Y0, A1 to Y1, A2 to Y2, and A3 to Y3). MUXCFG = 1 is the MUX/fanout mode. The
following table lists the MUX/fanout and buffer mode connections.
Table 1.
MUX Settings
MUXCFG = 1
MUXCFG = 0
SCK = 0 or 1
Primary Secondary
SCK = 0
SCK = 0
From To From To
From
A0
To
Y0
Y1
Y2
Y3
A0
A0
A2
A2
Y0
Y1
Y2
Y3
A1
A1
A3
A3
Y0
Y1
Y2
Y3
A1
A2
A3
The SCK pin is used for the serial clock in all register programming modes, but in static
configuration mode it is used as a control input that can be set high or low. When
changing from a programming mode to static configuration mode (or vice versa), it is
Revision 2.0
September 2010
Confidential
Page 12
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
