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VSC7111 Datasheet
Functional Descriptions
The output of the integrating amplifier increases when more ISE Short/Long is needed
relative to the ISE Gain. This signal is fed back to the ISE short, long, and gain stages
to adjust the equalization. The characteristics of the AEQ can be altered by changing
the AEQ Goal (Registers 15'h/60'h, bits 2:0) and by changing the AEQ Short/Long ratio
(Registers 15'h/60'h, bits 5:3). The AEQ Goal changes the ratio between the average
voltage amplitudes at AEQ Tap 2 and AEQ Tap 1. The AEQ Short/Long ratio changes the
feedback ratio between the ISE short and ISE long adjustment signals.
The following illustration shows the AEQ block diagram.
Figure 4.
Automatic (Adaptive) Equalizer Block Diagram
AEQ
Tap2
Voltage
Rectifier
High-Pass
Filter
AEQ Goal
Attenuator
Integrating
Amp
+
–
AEQ
Tap 1
Voltage
Rectifier
High-Pass
Filter
Inverting
Amp
–
ISE Gain
Adjust
ISE Long
Adjust
AEQ
Short/Long
Ratio
ISE Short
Adjust
2.9
Input Power and Termination Impedance
In register programming mode (two-wire or four-wire serial interface), the inputs are
turned off by default when the device is reset. The inputs can be powered on by
changing register 13'h/54'h bit 0 to 0. Each input is terminated to a 100 Ω differential
impedance. The input common-mode impedance can be adjusted by changing bit 1 of
register 13'h/54'h to support protocols such as PCI express. When bit 1 = 0, the input
common-mode impedance is approximately 3 kΩs. When bit 1 = 1, the common-mode
impedance is approximately 70 Ω. When the input is powered down, the common-mode
impedance is greater than 50 kΩ.
2.10
Input LOS
Each input has a loss of signal (LOS) detector associated with it that sets a bit high
whenever the signal level drops below a selected value. Although there is a time
component to the detection, the primary metric for asserting the LOS signal is the
signal amplitude. This amplitude is selectable in the registers on the Input LOS page
(14'h). For more information about the amplitude settings, see “Input LOS,” page 29.
The LOS signal is asserted upon a loss of signal and de-asserted when a signal is
present for more than 3 ns from when the signal level again exceeds the threshold. This
signal can be read from the registers on the channel status page (F0'h).
Revision 2.0
September 2010
Confidential
Page 19
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
