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VSC7111 Datasheet
Functional Descriptions
2
Functional Descriptions
The VSC7111 includes four high-speed differential input buffers and four high-speed
differential output buffers. Each of the four inputs includes an independent 0 dB to
30 dB equalizer that can be adjusted manually or configured for automatic (adaptive)
operation. Each of the four outputs includes 0 dB to 10 dB manually adjustable
pre-emphasis. The four 0 Gbps to 11.5 Gbps signal paths are asynchronous (no clock
signal or clock recovery) for data rate and protocol independent operation. Input and
output equalization settings can be configured statically by connecting control pins to
the supply voltage or ground, or the device can be programmed from an external
device using a two-wire (I2C) or four-wire (SPI) interface.
The following connection options are available:
•
Buffer: For straight through connections from each of the four inputs to its
corresponding output
•
MUX/fanout: Only two inputs are used and each one connects to two outputs. The
MUX/fanout option features automatic redundancy, which connects a secondary
input to the two outputs when a loss-of-signal (LOS) is detected at the primary
input.
A loss-of-signal (LOS) detector with programmable threshold is implemented at each of
the inputs. Upon LOS detection, the VSC7111 can optionally be configured to squelch
the corresponding output for applications such as SAS/SATA out-of-band (OOB)
signaling and PCI Express electrical idle. Additionally, when LOS is detected for more
than 1 ms, the input and its corresponding output can be configured to automatically
shut down in order to save power. Output squelching on LOS and input/output power
down on LOS are enabled by default at initial powerup.
PCI Express (PCIe) receiver detect is fully supported by the VSC7111. When this
function is enabled, the LOS status at the input is monitored to indicate electrical idle.
When LOS is asserted (PCIe electrical idle has been detected), the output sends out a
PCIe compliant common-mode pulse and monitors the rise time to determine whether
the line is terminated in a low impedance (receiver detected) or high impedance (no
receiver detected). The input common-mode impedance is then set low or high to
match the status detected by the transmitter. The receiver detect process is repeated
while LOS is asserted.
For data rates of 6.5 Gbps or lower, the VSC7111 can be set in the power-saving Green
mode by connecting the LOPWR pin high or through register access. Green mode
decreases the bandwidth of the internal core circuitry (output slew rate is not affected),
reducing the overall power requirements by approximately 25%.
2.1
Reset and Initialization
The VSC7111 is reset by an internal power-on reset (POR) circuit. The minimum
threshold for the POR circuit is approximately 2.2 V. It is important to design the
printed circuit board with sufficient decoupling capacitors to ensure that the supply
voltage never drops below this threshold. On reset, the VSC7111 defaults to the
configuration set by the status of the static control pins when the IFMODE1 and
IFMODE0 pins are high (static mode), or to the low-power state where all inputs and
outputs are off when the IFMODE pins are set to any one of the three serial interface
modes.
Revision 2.0
September 2010
Confidential
Page 11
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
