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VSC7111 Datasheet
Functional Descriptions
2.6
Four-Wire Serial Interface
When activated by a code of IFMODE[1:0] = 01, the chip will enter four-wire slave
serial mode. With the four-wire serial parallel interface (SPI) bus, signal SSB is the
active low serial select signal, which must be low to activate the port. Data is input to
the device on the signal MOSI (master out, slave in) and sampled on the falling edge of
clock signal SCK. Data is output on the signal MISO (master in, slave out) synchronous
with the rising edge of SCK. Each four-wire transaction is 3 bytes in length. An 8-bit
OPCODE is transferred first, which specifies whether a read (OP = 1) or write (OP = 0)
operation is to take place, followed by the 8-bit register address, finally followed by the
8-bit data word.
In single R/W mode, a single 8-bit data word is transferred. After the 8 bits are
transferred, the SSB line is brought high, indicating the end of the data transfer. If SSB
is brought high before all 8 bits in a given word are transferred, none of the 8 bits in
the word will be transferred.
The four-wire SPI serial bus is designed for applications where higher data transfer
rates are required. The four-wire interface has a maximum data transfer rate of
10 Mbps. Unlike the two-wire serial interface, the chip selection is done through an
active LOW serial select signal (SSB). When SSB is LOW, the VSC7111 will respond as a
slave device. When SSB is high, the SDA/MISO pin goes to a high impedance state.
The first programming instruction to the VSC7111 is used to enable the four-wire serial
interface. The programming instruction is in standard format and sets the address 79'h
to the value 01'h.
2.7
Power-Saving Green Mode
For data rates of 6.5 Gbps and lower, the VSC7111 can be set in the power saving
Green mode by connecting the LOPWR pin high or through register access. The Green
mode decreases the bandwidth of the internal core circuitry (output slew rate is not
affected), reducing the overall power requirements by approximately 25%.
Green mode can also be enabled from an external controller by using the serial
interface to modify internal register settings. The power modes can be customized
differently for each channel by using registers at pages 13'h and 22'h, or they can be
set equally for all channels using global registers 54'h and 58'h. In either case, bit 6 of
registers 13'h/54'h is set to 1 and bit 7 of registers 22'h/58'h is set to 1 to enable
register control of the power modes. Then bits 3:2 in registers 13'h/54'h are used to set
the input bandwidth/power level and bits 5:4 in registers 22'h/58'h are used to set the
output bandwidth/power level.
Excellent performance over the full 0-11.5G data rate range can be achieved with an
input bandwidth/power setting of bit 3 = 1 and bit 2 = 0 and an output bandwidth/
power setting of bit 5 = 0 and bit 4 = 1. In the Green mode, input and output
bandwidth/power settings are both set to 00.
2.8
Input Signal Equalization
Ten register pages are used to configure the four inputs. To configure the inputs, first
set the page to a number between 10'h and 19'h by writing to the current page register
7F'h, then access the desired input by writing to or reading from registers 00'h–03'h.
Revision 2.0
September 2010
Confidential
Page 17
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
