Advance Product Information
Subject to Change
VSC7111 Datasheet
Functional Descriptions
The following is an example sequence, assuming the serial interface address is set to
00'h:
Read: <S><00'h><A><Address><A><P>
Serial Addressing The VSC7111 two-wire serial interface supports a 7-bit slave
address. This address can be set either of two ways. The first is to hardwire the
appropriate SA[3:0] pins to VDD or GND, setting them high or low, in which case the
slave address is <000><SA[3:0]>, with SA[3:0] being the three least significant bits.
The second addressing method uses a proprietary interface that requires an additional
signal wire (SA3_SSB) and permits the address to be programmed on initialization.
When no address is programmed into the serial address register (it remains at its
default value of all zeroes), the SA[3:0] pin voltages define the permanent address for
the device. When a value other than all zeroes is programmed into the serial address
register, the new value overrides the value on the SA[3:0] pins and the three MSBs.
The SA3_SSB pin must be held high for programming the serial address register.
The serial address register does not latch a programmed value unless the SA3_SSB pin
is held high concurrent with the programming instruction, which means that the device
whose serial address register is being written will be accessed at an address between
08'h and 0F'h (depending on the states of the SA[2:0] pins) during that write
operation, following which the serial address register will have the new programmed
address.
2.5
Two-Wire Serial Interface, Master Mode
When activated by a code of IFMODE[1:0] = 10, the chip will drive SCK and use
SDA_MOSI to communicate with an external serial EEPROM and read the contents into
the internal register map of the VSC7111 to provide a loadable user configuration. The
global register space of the VSC7111 is not accessed during master mode as this would
overwrite any values already placed in the individual channel registers. Eleven bits of
EEPROM address space will contain all the data necessary to write to the VSC7111
individual register space. The two-wire serial master controller skips over unused
register space to speed the load time of the memory space.
The following table lists the memory layout of the EEPROM maps to the internal register
space.
Table 6.
Master Mode Address Mapping for EEPROM
Page Address Base Address EEPROM Address
(6 bits)
(5 bits)
(11 bits)
000–010'h
011–0FF'h
200–290'h
291–3FF'h
400–4B0'h
4B1–7FF'h
EEPROM Address Space
00–00'h
00–03'h
Used
Not used
Used
10–14'h
20–25'h
00–03'h
00–03'h
Not used
Used
Not used
Revision 2.0
September 2010
Confidential
Page 16
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
