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Table 448. Intel Asynchronous Mode – Read Cycle
D5
D6
TIAMCRDAD Delay from mpu_clk rise to rdy asserted
TIAMCDADD Delay from mpu_clk rise to data driven
16
6
ns
ns
4.2.16
Intel Asynchronous Mode—Write Cycle
This section provides information about the write cycle for the Intel asynchronous mode.
Figure 91. Intel Asynchronous Mode—Write Cycle
register_address
addr[11:0]
S0
H0
S5
ale
csn
wrn
H2
S2
S3
H3
D0
D5
D4
D1
rdy
Data
S4 H4
data[15:0]
mpu_clk
In the following table, all outputs drive a 30-pF load capacitance. Also, mpu_clk is synchronous to the
microprocessor clock.
Table 449. Intel Asynchronous Mode – Write Cycle
Label Symbol
Parameter
Minimum Typical Maximum Unit
S0
H0
S2
H2
TIAADALS
TIAALADH
TIACSMCS
Setup time from addr to ale fall
Hold time from ale de-asserted to addr
Setup time from csn asserted to mpu_clk rise
2
1
2
ns
ns
ns
ns
18
18
TIAWRCSDH Hold time from wrn de-asserted to csn
de-asserted
6
S3
H3
TIAWRMCS
Setup time from wrn asserted to mpu_clk rise
2
0
ns
ns
TIARDWRDH Hold time from rdy de-asserted to wrn
de-asserted
S4
H4
S5
D0
D1
D4
D5
TIADAMCS
TIAMCDATH
TIAALMCS
Setup time from data to mpu_clk rise
2
1
2
ns
ns
ns
ns
ns
ns
ns
Hold time from mpu_clk rise to data tri-state
Setup time from ale de-asserted to mpu_clk rise
50
16
6
TIAMCRDDD Delay from mpu_clk rise to rdy de-asserted
TIACSRDTD
TIAMCRDD
Delay from csn de-asserted to rdy tri-state
Delay from mpu_clk rise to rdy driven
6
TIAMCRDAD Delay from mpu_clk rise to rdy asserted
16
404 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
