VSC6134
Datasheet
4.2.12
Motorola Synchronous Mode—Write Cycle
This section provides information about the write cycle for the Motorola synchronous mode.
Figure 87. Motorola Synchronous Mode—Write Cycle
mpu_clk
S0
S1
addr[11:0]
tsn
register_address
S2
S3
csn
rwn
D0
D5
D4
D1
tan
S4
data[15:0]
Data
In the following table, all outputs drive a 30-pF load capacitance.
Table 445. Motorola Synchronous Mode—Write Cycle
Label
S0
Symbol
Parameter
Minimum Maximum Unit
TMSBADMCS
TMSBADDCH
TMSBTSMCS
Setup time from addr to mpu_clk rise
Hold time from addr to mpu_clk rise
2
1
2
ns
ns
ns
H0
S1
Setup time for tsn asserted/de-asserted to mpu_clk
rise
H1
S2
TMSBASMCH
TMSBCSMCS
Hold time for tsn asserted/de-asserted to mpu_clk rise
1
2
ns
ns
Setup time for csn asserted/de-asserted to mpu_clk
rise
S3
H3
S4
H4
D0
D1
D4
D5
TMSBRWMCS Setup time for rwn rise/fall to mpu_clk rise
TMSBRWMCH Hold time for rwn rise/fall to mpu_clk rise
2
1
2
1
ns
ns
ns
ns
ns
ns
ns
ns
TMSBDAMCS
TMSBDAMCH
TMSBASDTD
TMSBMCDTD
TMSBMCDTD
TMSBMCTAD
Setup time for data ready to mpu_clk rise
Hold time for data ready to mpu_clk rise
Delay from mpu_clk rise to tan de-asserted
Delay from mpu_clk fall to tan tristate
Delay from mpu_clk rise to tan driven
Delay from mpu_clk rise to tan asserted
16
6
6
16
400 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
