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Datasheet
4.2.13
Intel Synchronous Mode—Read Cycle
This section provides information about the read cycle for the Intel synchronous mode.
Figure 88. Intel Synchronous Mode—Read Cycle
mpu_clk
addr[11:0]
S0
S1
register_address
adsn
S2
csn
wrn
S3
D0
D3
D5
D2
D4
D1
rdyrcvn
data[15:0]
Data
In the following table, all outputs drive a 30-pF load capacitance.
Table 446. Intel Synchronous Mode—Read Cycle
Label
S0
Symbol
Parameter
Minimum Maximum Unit
TISADMCS
TISADMCH
TISASMCS
Setup time from addr to mpu_clk rise
Hold time from addr to mpu_clk rise
2
1
2
ns
ns
ns
H0
S1
Setup time for adsn asserted/de-asserted to mpu_clk
rise
H1
S2
S3
H3
D0
D1
D2
D3
D4
D5
TISASMCH
Hold time for adsn asserted/de-asserted to mpu_clk rise
1
2
2
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TISCSSMCS Setup time for csn asserted/de-asserted to mpu_clk rise
TISWRMCS
TISWRMCH
TISMCRDD
Setup time for wrn rise/fall to mpu_clk rise
Hold time for wrn rise/fall to mpu_clk rise
Delay from mpu_clk rise to rdyrcvn de-asserted
16
6
TISMCRDTD Delay from mpu_clk fall to rdyrcvn tristate
TISMCDAD Delay from mpu_clk rise to data ready
9
TISMCDATD Delay from mpu_clk rise to data tristate
TISMCRDDD Delay from mpu_clk rise to rdyrcvn driven
6
6
TISMCRDD
Delay from mpu_clk rise to rdyrcvn asserted
16
401 of 438
VMDS-10185 Revision 4.0
July 2006
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