VSC6134
Datasheet
Table 458. Microprocessor Interface Pins (continued)
Pin
Y1
Name
I/O Type
TI
Description
MPADDR0
MPDATA15
Microprocessor address bus. MPADDR11 is the MSB.
R3
TI /TO
Microprocessor bidirectional data bus. MPDATA15 is
the MSB.
R2
R1
N4
P3
P4
P2
P1
N3
N1
N2
L4
L3
K4
K2
K3
J2
MPDATA14
MPDATA13
MPDATA12
MPDATA11
MPDATA10
MPDATA9
MPDATA8
MPDATA7
MPDATA6
MPDATA5
MPDATA4
MPDATA3
MPDATA2
MPDATA1
MPDATA0
ADSN_ALE
TI /TO
TI /TO
TI /TO
TI /TO
TI /TO
TI /TO
TI /TO
TI /TO
TI /TO
TI /TO
TI /TO
TI /TO
TI /TO
TI /TO
TI /TO
TI
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Microprocessor bidirectional data bus.
Motorola Mode:
Microprocessor address strobe. Active low for one
MPU_CLK cycle for the Synchronous mode, and active
low for the entire read/write cycle for the
Pseudo-Synchronous mode. The address bus
(MPADDR[11:0]) should remain valid for the duration of
ADSN (the internal address latches are transparent
when ADSN is low).
Intel Mode:
Microprocessor address strobe. Active low for one
MPU_CLK cycle for the Synchronous mode .
Microprocessor address latch enable. Asynchronous
mode active high signal that latches the address bus
when it is low. When ALE is high, the internal address
latches are transparent.
408 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
