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Datasheet
Table 447. Intel Synchronous Mode—Write Cycle (continued)
Label
D4
Symbol
TISMCRDDD Delay from mpu_clk rise to rdyrcvn driven
TISMCRDD Delay from mpu_clk rise to rdyrcvn asserted
Parameter
Minimum Maximum Unit
6
ns
ns
D5
16
4.2.15
Intel Asynchronous Mode—Read Cycle
This section provides information about the read cycle for the Intel asynchronous mode.
Figure 90. Intel Asynchronous Mode—Read Cycle
register_address
addr[11:0]
ale
S0
H 0
S5
H 2
S2
S3
csn
rdn
H3
D0
D5
D2
D4
D6
D1
rdy
D3
data[15:0]
mpu_clk
Data
In the following table, all outputs drive a 30-pF load capacitance. Also, mpu_clk is synchronous to the
microprocessor clock.
Table 448. Intel Asynchronous Mode – Read Cycle
Label Symbol
Parameter
Minimum
Typical
Maximum Unit
S0
H0
S2
H2
TIAADALS
TIAALADH
TIACSMCS
Setup time from addr to ale fall
Hold time from ale de-asserted to addr
Setup time from csn asserted to mpu_clk rise
2
1
2
ns
ns
18
18
50
ns
ns
TIARDCSDH Hold time from rdn de-asserted to csn
de-asserted
6
S3
H3
TIARDMCS
Setup time from rdn asserted to mpu_clk rise
2
0
ns
ns
TIARDRDDH Hold time from rdy de-asserted to rdn
de-asserted
S5
TIAALMCS
Setup time from ale de-asserted to mpu_clk
rise
2
ns
D0
D1
D2
D3
D4
TIAMCRDDD Delay from mpu_clk rise to rdy de-asserted
16
6
ns
ns
ns
ns
ns
TIACSRDTD
TIAMCDAD
TIARDDATD
TIAMCRDD
Delay from csn de-asserted to rdy tri-state
Delay from mpu_clk rise to data ready
Delay from rdn de-asserted to data tri-state
Delay from mpu_clk rise to rdy driven
9
8
6
403 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
