VSC6134
Datasheet
5
Pin Descriptions
The VSC6134 device has 897 pins, which are described in this section.
The following table provides descriptions of the I/O types used in this section.
Table 457. Description of I/O Types
I/O Type
TI
Description
LVTTL input buffer
LVTTL output buffer
TO
LIT
LVDS input buffer with on-chip 100-Ω terminations between PAD and
PADN
LIC
LO
LVDS Input buffer in single-ended CMOS mode (PON de-asserted)
LVDS output buffer; requires external 100-Ω terminations between the
differential inputs of the far-end receiver (PAD and PADN)
ODO
TP
Open drain output buffer implemented using a LVTTL output buffer
Internal node
GND
VDD
VDDIO
Ground pin
Supply pin for VDD
I/O supply pin for VDD
5.1
Pin Identifications
This section contains the pin descriptions for the VSC6134 device.
5.1.1
Microprocessor Interface Pins
The following table contains the descriptions for the microprocessor interface pins.
Table 458. Microprocessor Interface Pins
Pin
R4
T1
Name
I/O Type
Description
MPADDR11
MPADDR10
MPADDR9
MPADDR8
MPADDR7
MPADDR6
MPADDR5
MPADDR4
MPADDR3
MPADDR2
MPADDR1
TI
TI
TI
TI
TI
TI
TI
TI
TI
TI
TI
Microprocessor address bus. MPADDR11 is the MSB.
Microprocessor address bus.
Microprocessor address bus.
Microprocessor address bus.
Microprocessor address bus.
Microprocessor address bus.
Microprocessor address bus.
Microprocessor address bus.
Microprocessor address bus.
Microprocessor address bus.
Microprocessor address bus.
T2
U2
U1
U3
V2
V3
W2
W1
W3
407 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
