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Datasheet
4.2.14
Intel Synchronous Mode—Write Cycle
This section provides information about the write cycle for the Intel synchronous mode.
Figure 89. Intel Synchronous Mode—Write Cycle
mpu_clk
S0
addr[11:0]
register_address
S1
adsn
S2
csn
wrn
S3
D0
D5
D4
D1
rdyrcvn
S4
data[15:0]
Data
In the following table, all outputs drive a 30-pF load capacitance.
Table 447. Intel Synchronous Mode—Write Cycle
Label
S0
Symbol
Parameter
Minimum Maximum Unit
TISADMCS
TISADMCH
TISASMCS
Setup time from addr to mpu_clk rise
Hold time from addr to mpu_clk rise
2
1
2
ns
ns
ns
H0
S1
Setup time for adsn asserted/de-asserted to mpu_clk
rise
H1
S2
S3
H3
S4
H4
D0
D1
TISASMCH
Hold time for adsn asserted/de-asserted to mpu_clk rise
1
2
2
1
2
1
ns
ns
ns
ns
ns
ns
ns
ns
TISCSSMCS Setup time for csn asserted/de-asserted to mpu_clk rise
TISWRMCS
TISWRMCH
TISDAMCS
TISDAMCH
TISMCRDD
Setup time for wrn rise/fall to mpu_clk rise
Hold time for wrn rise/fall to mpu_clk rise
Setup time for data ready to mpu_clk rise
Hold time for data ready to mpu_clk rise
Delay from mpu_clk rise to rdyrcvn de-asserted
16
6
TISMCRDTD Delay from mpu_clk fall to rdyrcvn tristate
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VMDS-10185 Revision 4.0
July 2006
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