VSC6134
Datasheet
4.2.11
Motorola Synchronous Mode—Read Cycle
This section provides information about the read cycle for the Motorola synchronous mode.
Figure 86. Motorola Synchronous Mode—Read Cycle
mpu_clk
addr[11:0]
S0
S1
register_address
tsn
S2
csn
S3
rwn
D0
D3
D5
D2
D4
D1
tan
data[15:0]
Data
In the following table, all outputs drive a 30-pF load capacitance.
Table 444. Motorola Synchronous Mode—Read Cycle
Label
S0
Symbol
Parameter
Minimum Maximum Unit
TMSBADMCS
TMSBADDCH
TMSBTSMCS
Setup time from addr to mpu_clk rise
Hold time from addr to mpu_clk rise
2
1
2
ns
ns
ns
H0
S1
Setup time for tsn asserted/de-asserted to mpu_clk
rise
H1
S2
TMSBASMCH
Hold time for tsn asserted/de-asserted to mpu_clk rise
1
2
ns
ns
TMSBCSSMCS Setup time for csn asserted/de-asserted to mpu_clk
rise
S3
H3
D0
D1
D2
D3
D4
D5
TMSBRWMCS
TMSBRWMCH
TMSBASDTD
TMSBMCDTD
TMSBMCDAD
TMSBMCDAD
TMSBMCDTD
TMSBMCTAD
Setup time for rwn rise/fall to mpu_clk rise
Hold time for rwn rise/fall to mpu_clk rise
Delay from mpu_clk rise to tan de-asserted
Delay from mpu_clk fall to tan tristate
Delay from mpu_clk rise to data ready
Delay from mpu_clk rise to data tristate
Delay from mpu_clk rise to tan driven
Delay from mpu_clk rise to tan asserted
2
1
ns
ns
ns
ns
ns
ns
ns
ns
16
6
9
6
6
16
399 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
