VSC6134
Datasheet
4.2.10
Motorola Pseudo-Synchronous—Write Cycle
This section provides information about the write cycle for the Motorola pseudo-synchronous mode.
Figure 85. Motorola Pseudo-Synchronous Mode—Write Cycle
mpu_clk
addr[11:0]
register_address
S1
S0
S3
S1
asn
csn
rwn
S2
D5
D1
D4
D0
dtkn
S4
data[15:0]
Data
In the following table, all outputs drive a 30-pF load capacitance.
Table 443. Motorola Pseudo-Synchronous Mode—Write Cycle
Label
S0
Symbol
Parameter
Minimum Maximum
Unit
ns
TMSAADASS
TMSAADASH
TMSAASMCS
Setup time from addr ready to asn asserted
Hold time from addr ready to asn asserted
2
1
2
H0
S1
ns
Setup time for asn asserted/de-asserted to
mpu_clk fall
ns
H1
S2
TMSAASMCH
TMSACSMCS
Hold time for asn asserted/de-asserted to
mpu_clk fall
1
2
ns
ns
Setup time for csn asserted/de-asserted to
mpu_clk rise
S3
H3
S4
H4
D0
TMSARWMCS
TMSARWMCH
TMSADAMCS
TMSADAMCH
TMSAASDTD
Setup time for rwn rise/fall to mpu_clk rise
Hold time for rwn rise/fall to mpu_clk rise
Setup time for data ready to mpu_clk rise
Hold time for data ready to mpu_clk rise
2
ns
ns
ns
ns
ns
1
2
1
Delay from asn de-asserted to dtkn
de-asserted
10
D1
D4
D5
TMSAMCDTTD
TMSAMCDTD
TMSAMCDTAD
Delay from mpu_clk fall to dtkn tristate
Delay from mpu_clk rise to dtkn driven
Delay from mpu_clk rise to dtkn asserted
6
6
8
ns
ns
ns
398 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
