VSC6134
Datasheet
4.2.9
Motorola Pseudo-Synchronous Mode—Read Cycle
This section provides information about the read cycle for the Motorola pseudo-synchronous mode.
Figure 84. Motorola Pseudo-Synchronous Mode—Read Cycle
mpu_clk
addr[11:0]
register_address
S1
S0
S1
asn
csn
rwn
S2
S3
D1
D4
D5
D2
D0
dtkn
D3
data[15:0]
Data
In the following table, all outputs drive a 30-pF load capacitance.
Table 442. Motorola Pseudo-Synchronous Mode—Read Cycle
Label
S0
Symbol
Parameter
Minimum Maximum Unit
TMSAADASS
TMSAADASH
TMSAASMCS
Setup time from addr ready to asn asserted
Hold time from addr ready to asn asserted
2
1
2
ns
ns
ns
H0
S1
Setup time for asn asserted/de-asserted to
mpu_clk fall
H1
S2
TMSAASMCH
TMSACSMCS
Hold time for asn asserted/de-asserted to
mpu_clk fall
1
2
ns
ns
Setup time for csn asserted/de-asserted to
mpu_clk rise
S3
H3
D0
D1
D2
D3
D4
D5
TMSARWMCS
TMSARWMCH
TMSAASDTD
TMSAMCDTTD
TMSAMCDAD
TMSAASDAD
TMSAMCDTD
TMSAMCDTAD
Setup time for rwn rise/fall to mpu_clk rise
Hold time for rwn rise/fall to mpu_clk rise
Delay from asn de-asserted to dtkn de-asserted
Delay from mpu_clk fall to dtkn tristate
Delay from mpu_clk rise to data ready
Delay from asn de-asserted to data tristate
Delay from mpu_clk rise to dtkn driven
Delay from mpu_clk rise to dtkn asserted
2
1
ns
ns
ns
ns
ns
ns
ns
ns
10
6
9
6
6
8
397 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
