VSC6134
Datasheet
3.8.86
Enhanced FEC Corrected One Bit Error Count (LSW)
Address:
0x764
Register Reset Value:
0x0000
Table 287. Enhanced FEC Corrected One Bit Error Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC_ONE_ERR_LWR
RO
Count of total number of corrected one errors (lower 16 bits
of 32 bit count). “Performance Monitoring,’ page 119
0x0000
3.8.87
Enhanced FEC Corrected One Bit Error Count (MSW)
Address:
0x765
Register Reset Value:
0x0000
Table 288. Enhanced FEC Corrected One Bit Error Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC_ONE_ERR_UPR
RO
Count of total number of corrected one errors (upper 16 bits
of 32 bit count). “Performance Monitoring,’ page 119
0x0000
3.8.88
Enhanced FEC Corrected Zero Bit Error Count (LSW)
Address:
0x766
Register Reset Value:
0x0000
Table 289. Enhanced FEC Corrected Zero Bit Error Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC_ZERO_ERR_LWR
RO
Count of total number of corrected zero errors (lower 16
bits of 32 bit count). “Performance Monitoring,’ page 119
0x0000
3.8.89
Enhanced FEC Corrected Zero Bit Error Count (MSW)
Address:
0x767
Register Reset Value:
0x0000
Table 290. Enhanced FEC Corrected Zero Bit Error Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC_ZERO_ERR_UPR
RO
Count of total number of corrected zero errors (upper
16 bits of 32 bit count). “Performance Monitoring,’
page 119
0x0000
319 of 438
VMDS-10185 Revision 4.0
July 2006