VSC6134
Datasheet
3.8.90
DW PSI Monitor Configuration Register
Address:
0xF70: Add Path
0x770: Drop Path
0x001F
Register Reset Value:
Table 291. DW PSI Monitor Configuration Register
Reset
Value
Bit
15
Name
Access
RO
Description
Reserved
PSI_MPNT
0
14:8
R/W
PSI MPU read pointer.
0x00
This is the MPU read pointer into the PSI FIFO that
auto-increments on an MPU read or write.
7
PSI_INVD
R/W
PSI invalidate.
0
A zero to one transition clears the two PSI live bits
(0xF05 add, 0x705 drop), invalidating both PSI fields.
6
Reserved
PSI_MAT
RO
0
5:3
R/W
PSI match.
011
These bits determine the consecutive number of matching
PSI fields before setting the respective PSI live bits active,
indicating a valid field. 0 through 7 values correspond to 1
through 8 matches.
2:0
PSI_MIS
R/W
PSI mismatch.
111
These bits determine, when the respective live bits are
active, the consecutive number of mismatching PSI fields
before clearing the respective live bits. 0 through 7 values
correspond to 1 through 8 mismatches.
320 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
