VSC6134
Datasheet
3.8.71
Enhanced FEC 3 Uncorrectable Code Word Count (MSW)
Address:
0x747
Register Reset Value:
0x0000
Table 272. Enhanced FEC 3 Uncorrectable Code Word Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC3_UCW_UPR
RO
Count of total number of uncorrectable code words from
EFEC decoder 3 (upper 16 bits of 32 bit count)
0x0000
3.8.72
Enhanced FEC 4 Uncorrectable Code Word Count (LSW)
Address:
0x748
Register Reset Value:
0x0000
Table 273. Enhanced FEC 4 Uncorrectable Code Word Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC4_UCW_LWR
RO
Count of total number of uncorrectable code words from
EFEC decoder 4 (lower 16 bits of 32 bit count). This is the
last of the four decoders.
0x0000
3.8.73
Enhanced FEC 4 Uncorrectable Code Word Count (MSW)
Address:
0x749
Register Reset Value:
0x0000
Table 274. Enhanced FEC 4 Uncorrectable Code Word Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC4_UCW_UPR
RO
Count of total number of uncorrectable code words from
EFEC decoder 4 (upper 16 bits of 32 bit count).This is the
last of the four decoders.
0x0000
3.8.74
Enhanced FEC 1 Corrected Bit Error Count (LSW)
Address:
0x74A
Register Reset Value:
0x0000
Table 275. Enhanced FEC 1 Corrected Bit Error Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC1_ERR_LWR
RO
Count of total number of correctable bit errors from EFEC
decoder 1 (lower 16 bits of 32 bit count)
0x0000
315 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
