VSC6134
Datasheet
3.8.83
Standard FEC Corrected One Bit Error Count (MSW)
Address:
0xF61: Add Path
0x761: Drop Path
0x0000
Register Reset Value:
Table 284. Standard FEC Corrected One Bit Error Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
StFEC_ONE_ERR_UPR
RO
Count of total number of corrected one bit errors (upper
16 bits of 32 bit count). “Performance Monitoring,’
page 119
0x0000
3.8.84
Standard FEC Corrected Zero Bit Error Count (LSW)
Address:
0xF62: Add Path
0x762: Drop Path
0x0000
Register Reset Value:
Table 285. Standard FEC Corrected Zero Bit Error Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
StFEC_ZERO_ERR_LWR
RO
Count of total number of corrected zero errors (lower
16 bits of 32 bit count). “Performance Monitoring,’
page 119
0x0000
3.8.85
Standard FEC Corrected Zero Bit Error Count (MSW)
Address:
0xF63: Add Path
0x763: Drop Path
0x0000
Register Reset Value:
Table 286. Standard FEC Corrected Zero Bit Error Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
StFEC_ZERO_ERR_UPR
RO
Count of total number of corrected zero errors (upper
16 bits of 32 bit count). “Performance Monitoring,’
page 119
0x0000
318 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
