VSC6134
Datasheet
3.8.75
Enhanced FEC 1 Corrected Bit Error Count (MSW)
Address:
0x74B
Register Reset Value:
0x0000
Table 276. Enhanced FEC 1 Corrected Bit Error Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC1_ERR_UPR
RO
Count of total number of correctable bit errors from EFEC
decoder 1 (upper 16 bits of 32 bit count)
0x0000
3.8.76
Enhanced FEC 2 Corrected Bit Error Count (LSW)
Address:
0x74C
Register Reset Value:
0x0000
Table 277. Enhanced FEC 2 Corrected Bit Error Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC2_ERR_LWR
RO
Count of total number of correctable bit errors from EFEC
decoder 2 (lower 16 bits of 32 bit count)
0x0000
3.8.77
Enhanced FEC 2 Corrected Bit Error Count (MSW)
Address:
0x74D
Register Reset Value:
0x0000
Table 278. Enhanced FEC 2 Corrected Bit Error Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC2_ERR_UPR
RO
Count of total number of correctable bit errors from EFEC
decoder 2 (upper 16 bits of 32 bit count)
0x0000
3.8.78
Enhanced FEC 3 Corrected Bit Error Count (LSW)
Address:
0x74E
Register Reset Value:
0x0000
Table 279. Enhanced FEC 3 Corrected Bit Error Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC3_ERR_LWR
RO
Count of total number of correctable bit errors from EFEC
decoder 3 (lower 16 bits of 32 bit count)
0x0000
316 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
