VSC6134
Datasheet
3.8.79
Enhanced FEC 3 Corrected Bit Error Count (MSW)
Address:
0x74F
Register Reset Value:
0x0000
Table 280. Enhanced FEC 3 Corrected Bit Error Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC3_ERR_UPR
RO
Count of total number of correctable bit errors from EFEC
decoder 3 (upper 16 bits of 32 bit count)
0x0000
3.8.80
Enhanced FEC 4 Corrected Bit Error Count (LSW)
Address:
0x750
Register Reset Value:
0x0000
Table 281. Enhanced FEC 4 Corrected Bit Error Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC4_ERR_LWR
RO
Count of total number of correctable bit errors from EFEC
decoder 4 (lower 16 bits of 32 bit count)
0x0000
3.8.81
Enhanced FEC 4 Corrected Bit Error Count (MSW)
Address:
0x751
Register Reset Value:
0x0000
Table 282. Enhanced FEC 4 Corrected Bit Error Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
EFEC4_ERR_UPR
RO
Count of total number of correctable bit errors from EFEC
decoder 4 (upper 16 bits of 32 bit count)
0x0000
3.8.82
Standard FEC Corrected One Bit Error Count (LSW)
Address:
0xF60: Add Path
0x760: Drop Path
0x0000
Register Reset Value:
Table 283. Standard FEC Corrected One Bit Error Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
StFEC_ONE_ERR_LWR
RO
Count of total number of corrected one bit errors (lower
16 bits of 32 bit count). “Performance Monitoring,’ page 119
0x0000
317 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
