VSC6134
Datasheet
3.8.91
DW PSI FIFO Access Register
Address:
0xF71: Add Path
0x771: Drop Path
0x0000
Register Reset Value:
Table 292. DW PSI FIFO Access Register
Reset
Value
Bit
Name
Access
Description
15:0
PSI
RO
This register provides access to a 128 word deep, 16 bit
wide FIFO that holds the monitored PSI values. The FIFO
has one configurable pointer for both read and write
operations shown in Table 291. Each time a read or write
operation occurs at this address (0xF71 Add / 0x771 Drop)
the pointer is automatically incremented by 1. Each of the
128 registers in the FIFO contains two 8-bit values for PSI.
Received PSI values are entered into the FIFO on a
rotating basis. The value of bits [7:0] of address 0000000 of
the FIFO represents PSI 0 and the value at bits [15:8] of
address 1111111 of the FIFO represents PSI 255. The
256-byte PSI signal is aligned with the OTU multiframe
(MFAS). Byte 0 of the 256-byte PSI signal is present at
OTU multiframe position 00.
0x0000
3.8.92
Framed PRBS Error Count Register (MSW)
Address:
0xF72: Add Path
0x772: Drop Path
0x0000
Register Reset Value:
Table 293. Framed PRBS Error Count Register (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
FPRBSERRCNT[31:16]
RO
Framed PRBS error counter MSW.
0x0000
3.8.93
Framed PRBS Error Count Register (LSW)
Address:
0xF73: Add Path
0x773: Drop Path
0x0000
Register Reset Value:
Table 294. Framed PRBS Error Count Register (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
FPRBSERRCNT[15:0]
RO
Framed PRBS error counter LSW.
0x0000
321 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
