VSC6134
Datasheet
3.7.9
RLL Justification Interval Register
Address:
0x332
Register Reset Value:
0x0000
Table 199. RLL Justification Interval Register
Reset
Value
Bit
Name
Access
Description
15:0
JUS_INTERVAL
RO
Measure of time, as a count of G.709 OTU frames
(~12.2 μs), between the previous two FIFO pointer actions.
FIFO pointer action is taken when received positive
justifications minus negative justifications equal 8. See bit
JUS_DIR for a direction of the justification.
0x0000
3.7.10
RLL Justification Reversal Direction Register
Address:
0x333
Register Reset Value:
0x3F00
Table 200. RLL Justification Reversal Direction Register
Reset
Value
Bit
15:6
5
Name
Access
RO
Description
Reserved
JUS_DIR
0xFC
0
RO
Indicates the direction of the FIFO pointer action noted by
the RLL_JUS bit and associated with the JUS_INTERVAL
register. A 1 indicates 8 accumulated positive justifications
and a 0 indicates negative.
4:0
Reserved
RO
0x00
3.7.11
VCO Mode Control Register
Address:
0x336
Register Reset Value:
0x4FC0
Table 201. VCO Mode Control Register
Reset
Value
Bit
Name
Access
Description
15:14
VCO_MODE
R/W
00: RLL mode
01: PFD mode
10: Reserved
11: Reserved
01
13:0
Reserved
RO
0xFC0
279 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
