VSC6134
Datasheet
3.7.7
RLL Lock Condition Mask Register
Address:
0x330
Register Reset Value:
0xF000
Table 197. RLL Lock Condition Mask Register
Reset
Value
Bit
Name
Access
Description
15
RLL_JUSM
R/W
1: Interrupt for RLL_JUS is masked.
1
0: Interrupt for RLL_JUS is not masked.
14
13
Reserved
1
1
RLL_WIN_CONVM
R/W
R/W
RO
1: Interrupt for RLL_WIN_CONV is masked.
0: Interrupt for RLL_WIN_CONV is not masked.
12
RLL_BP_CONVM
Reserved
1: Interrupt for RLL_BP_CONV is masked.
0: Interrupt for RLL_BP_CONV is not masked.
1
11:0
0x000
3.7.8
RLL Lock Condition Status Register
Address:
0x331
Register Reset Value:
0x0000
Table 198. RLL Lock Condition Status Register
Reset
Value
Bit
Name
Access
Description
15
RLL_JUSS
R/W
Indicates FIFO pointer action taken when received positive
justifications minus negative justifications equal 8. The
resulting adjustment can be in the positive or negative
direction as indicated by the JUS_DIR bit.
0
14
13
Reserved
RO
0
0
RLL_WIN_CONVS
R/W
Window convergence indication: window threshold is ≤ 2×
minimum window size.
Together with bit 12, can be used as RLL lock indication
when both are set to 1.
12
RLL_BP_CONVS
Reserved
R/W
RO
Beat period convergence: beat period threshold
≥ maximum beat period.
Together with bit 13, can be used as RLL lock indication
when both are set to 1.
0
11:0
0x000
278 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
