VSC6134
Datasheet
3.8.5
DW Overhead Monitor Interrupt Mask Register 0
Address:
0xF02: Add Path
0x702: Drop Path
0xFF00
Register Reset Value:
Table 206. DW Overhead Monitor Interrupt Mask Register 0
Reset
Value
Bit
Name
Access
Description
15
OOMM
R/W
1: Interrupt for OOM is masked.
1
0: Interrupt for OOM is not masked.
14
13
12
11
10
9
LOMM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
1: Interrupt for LOM is masked.
0: Interrupt for LOM is not masked.
1
APSPCCM
GCC_RDYM
OTU_AISM
GAISM
1: Interrupt for APSPCC is masked.
0: Interrupt for APSPCC is not masked.
1
1: Interrupt for GCC_RDY is masked.
0: Interrupt for GCC_RDY is not masked.
1
1
1: Interrupt for OTU_AIS is masked.
0: Interrupt for OTU_AIS is not masked.
1: Interrupt for GAIS is masked.
0: Interrupt for GAIS is not masked.
1
FPRBSSYNCM
FPRBSERRM
Reserved
1: Interrupt for FPRBSSYNC is masked.
0: Interrupt for FPRBSSYNC is not masked.
1
8
1: Interrupt for FPRBSERR is masked.
0: Interrupt for FPRBSERR is not masked.
1
7:0
0x00
3.8.6
DW Overhead Monitor Status Register 0
Address:
0xF03: Add Path
0x703: Drop Path
0x00C0
Register Reset Value:
Table 207. DW Overhead Monitor Status Register 0
Reset
Value
Bit
Name
Access
Description
15
OOMS
R/W
Out-of-multiframe alignment status.
A change in multiframe alignment sets this bit.
0
0
0
14
13
LOMS
R/W
R/W
Loss-of-multiframe alignment status.
A change in the loss-of-multiframe condition sets this bit.
APSPCCS
APS/PCC status.
The loading of new APS/PCC bytes or receiving invalid
APS/PCC bytes sets this bit.
282 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
